Modern high-density integrated circuits (ICs) are known to be vulnerable to damage from the electrostatic discharge (ESD) from a charged body (human or otherwise) as the charged body physically contacts the IC. ESD damage occurs when the amount of charge exceeds the capability of the electrical conduction path through the IC. The typical ESD failure mechanisms include thermal runaway resulting in junction shorting, and dielectric breakdown resulting in gate junction shorting in the metal-oxide-semiconductor (MOS) context.
An IC may be subjected to a damaging ESD event in the manufacturing process, during assembly, testing, or during runtime of the system in which the IC is installed. Some ESD protection schemes use active clamp circuits to shunt ESD current between the power supply rails and thereby protect internal IC element nodes that are connected to bond pads from ESD damage. An active clamp circuit may include a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) coupled between the power supply rails. This MOSFET is relatively large and often occupies 60% or more of total area of the ESD protection circuit. Each of the IC's pins generally includes its own ESD protection circuit with its own large MOSFET.